In modern integrated circuit technologies, numerous interconnect fabrication methodologies have been provided in order to interconnect integrated circuit devices. More particularly, some local interconnect methods have been implemented in the construction of very large scale integration (VLSI) and ultra large scale integration (ULSI) circuit environments. A specific concern in fabrication of VLSI and ULSI circuits has been the methods used to interconnect devices which are local to one another. A relevant example is efficient interconnection of the transistors in the memory cells of the static random access memory (SRAM) chips for reduced cell layout area. One current device interconnection method suffers inefficiencies by requiring numerous process steps and wasting excess unreacted refractory metal (and/or metal nitride) materials. An alternative known method based on the refractory metal nitride local interconnect technology can reduce the chip size but can be problematic because it utilizes interconnecting materials such as refractory metal nitrides which usually have a high electrical resistivity. The metal nitride local interconnect technology reduces the overall circuit speed and limits the maximum distance over which the interconnect may extend. Both of these methods also rely on complex fabrication processes which may cause process reproducibility and manufacturing yield degradation problems.
A first type of interconnection scheme existing in the prior art involves forming self-aligned refractory metal silicide contacts on a device while discarding, and therefore wasting, any excess material (either reacted metal nitride or unreacted) which extends over the insulating regions beyond the dimensions of the active device area. Additionally, a selective etch must be utilized in order to remove areas of unreacted metal and/or reacted metal nitride material. Further, this etch must be highly selective to prevent etching of reacted metal silicide and surrounding insulator layers. Thereafter, an interlevel dielectric is deposited over the device and contact holes are formed therein using standard photolighographic and etch processes. Finally, a metal layer (e.g. tungsten or aluminum) is deposited thereby forming electrical contacts between the top metal layer and the refractory metal silicide contacts . previously formed. A barrier layer such as sputtered or chemical-vapor-deposited titanium nitride may be used between the reacted silicide and top metal layers in order to improve the metallization reliability.
A second type of interconnection scheme known in the art involves forming self-aligned refractory metal silicide contacts on the device and retaining the selected portions of reacted refractory metal nitride (and/or unreacted refractory metal) material which are formed during refractory metal silicide formation process, and which extend over the insulator surfaces beyond the active dimensions of the interconnected device. This interconnection technique employs a microlithographic masking step and a subsequent selective anisotropic etch to form a specified pattern and maintain selected portions of the refractory material not converted to silicide. These selected portions, usually made of refractory metal nitrides, are thereafter used as local interconnects; however these portions have a high electrical resistivity because they have not reacted with a semiconductor material as have the silicide contacts on the active devices. This high resistivity material can limit the practical maximum interconnect length and efficiency of this type of local interconnect, particularly in the scaled submicron-technologies.
Therefore, a need has arisen for a method and structure involving the interconnection of semiconductor devices, which optimizes the local interconnection method and process and eliminates the problems identified above.